1. Field of the Invention
The invention relates generally to microelectronic interconnects and, in particular, to flip chip methods of interconnecting microelectronic components, and assemblies resulting therefrom.
2. Background of the Related Art
Electronic devices commonly include one or more semiconductor integrated circuit (IC) chips mounted on a circuit board. These semiconductor IC chips, sometimes referred to as “microchips,” are mounted such that electrical connections are made between the chips and the circuit board. Several techniques have been developed over the years to mount chips on a circuit board, including so-called wire bonding and flip chip techniques.
In the case of wire bonding, the chips are connected to the circuit board via mechanical carriers. The chips are configured to be mounted on the mechanical carriers and interconnected using wire bonds. More specifically, the chips are formed with metal pads or contacts on the active surface and are placed in the carriers with the pads facing outwardly so that metal wires can be bonded to these pads. The mechanical carriers are in turn connected to the circuit board by a plurality of pins leading from the wire bonds. This technique, while effective for some purposes, has several drawbacks. For one thing, the presence of the mechanical carrier increases the size of the device, making the wire bonding technique unsuitable for applications requiring the smallest possible footprint. Further, the length of the wires needed to connect the chips to the carrier can create levels of inductive reactance and radiation that are too high for certain applications.
The flip chip mounting technique was developed in the 1960's to form connections between silicon IC chips and circuit boards without the use of wire bonds. The technique involves forming a series of solder bumps on the active side of the chip to form metallurgical interconnections with metal bond sites on the board. More specifically, the active side of the integrated circuit is flipped upside down to facilitate contact between the bumps on the chip and the metal bond sites on the board. A soldering flux is typically used to remove metal oxides and promote wetting of the solder when the assembly is heated above the temperature of the solder. This process is referred to as reflow soldering.
FIGS. 1a-1c illustrate some common flip chip designs. In each case, it will be observed that the flip chip technique allows for an extremely compact package. Further, because the length of the interconnect is shorter in the flip chip design, there is a lower level of inductive reactance which leads to wider bandwidth performance and a lessening of the tuning required.
FIG. 1a shows an example of a solder bump connection flip chip interconnect. In this flip chip design, a silicon microchip 201 layered with a dielectric material 203 and fitted with a piece of under bump metal which acts as a conductive bond pad 205. Further, the substrate 211 to which the silicon microchip 201 is attached is also fitted with a bond pad 209. Between the bond pads 205 and 209 is placed a solder ball 207 which acts as the conductive interconnect between the silicon microchip 201 and the substrate 211.
FIG. 1b shows a soldered metal stud connection flip chip interconnect. In this flip chip design a silicon microchip 301 is again layered with a dielectric material 303 and fitted with a piece of under bump metal which acts as a conductive bond pad 305. Again the substrate 313 is also fitted with a bond pad 311. A portion of conductive solder or epoxy 309 is placed on the substrate bond pad 311. A metal ball 307 completes the connection between the silicon microchip 301 and the substrate 313.
FIG. 1c shows a thermal compression or ultrasonic bonded gold stud bump connection flip chip interconnect. In this flip chip design, a silicon microchip 401 has a bond pad 403, and a substrate 409 also has a corresponding bond pad 407. The connection between the corresponding bond pads is achieved by placing a gold ball 405 between the bond pads 403, 407 and applying either heat and pressure or ultrasonic energy in the appropriate degree.
While these flip chip interconnect designs have proven effective for use with silicon microchips, they have not been effective for use with GaAs integrated circuits that process high frequency radio frequency (“RF”) and millimeter wave (“MMW”) signals. The specific deficiencies are as follows.
First, GaAs wafers do not have the mechanical strength necessary to survive conventional flip chip techniques. The silicon wafers used in prior art flip chip designs have generally been 15 mils in thickness, this level of thickness provided the silicon flip chips with a high level of mechanical strength necessary to withstand the prior art implementations of flip chip interconnects. However, a typical GaAs microchip is a mere 4 mils thick, and is therefore prone to cracking during flip chip assembly. This is especially true when the assembly is done by way of thermal compression which uses extreme force to bond the flip chip to the substrate with many stud bumps. Stud bumps are pieces of metal or solder which act as connectors between the bond pads of the flip chip and the bond pads of the substrate. In addition to the weakness caused by the lack of thickness, GaAs has a lower intrinsic fracture strength than silicon, meaning that even if a GaAs and silicon microchip were the same thickness the GaAs microchip would be weaker due to inherent physical properties. While thicker GaAs circuit designs have been proposed in order to compensate for the above discussed weakness, they are not acceptable for thermal dissipation in many applications due to the much lower thermal conductivity of GaAs as compared to Silicon. Further, thicker GaAs microchips have been prone to unwanted signal moding in MMW microchip designs. Thicker GaAs (e.g. 25 mils) and the associated high dielectric constant (12.9) result in lower cutoff frequencies of the various order RF modes defined by the structure. Energy can be lost and distorted by these modes at the desired operating frequencies if the cutoff frequency for the higher order mode is less than the operating frequency.
Further, the poor thermal conductivity of GaAs in relation to silicon presents certain difficulties. The silicon wafers used in prior art flip chip designs have higher thermal conductivity properties than does GaAs. Because GaAs microchips have poor thermal conductivity properties they are typically soldered to heat spreaders with high temperature gold/tin solder in an effort to minimize device junction temperature. During this high temperature process, the solder bump balls, generally applied at the wafer level before singulation, used to connect the GaAs microchip to the substrate become molten and any scrubbing motion or weight that is generally required to achieve void free solder could easily impair these molten solder bump balls. Thus, the thermal conductivity properties of GaAs make its use in prior art flip chip interconnect designs difficult. Additionally soldering hard gold stud bump interconnects that might be envisioned to solve this problem instead form an intermetallic alloy with lead tin solder resulting in a very weak solder joint. Other solder choices have chronic problems as well involving joints that are extremely brittle and weak, have too low of a melting temperature, or are environmentally sensitive as with Indium based solders.
Accurate probe performance testing of low frequency silicon requires an individual ground-signal-ground probe needle make contact. However, accurate RF probing of GaAs substrates requires precision three point coplanar impedance controlled contacts. Therefore, non-uniform bump height can result in one or more of the ground-signal-ground probe needles not making contact, thereby impairing the measurement results. Bump spacing will also vary the impedance of the ground-signal-ground interface, thus impairing the measurement results further.
Substrates generally used to integrate flip chip silicon microchips are too lossy for RF applications. Examples of these lossy materials are FR-4, Polyimide, high temperature co-fired ceramic (“HTCC”), and 351 low temperature co-fired ceramic (“LTCC”). Fortunately, emerging materials, such as 943 LTCC and Ferro LTCC, that have significantly lower RF loss, especially at MMW frequencies are being developed for high density routing. These materials require use of metal systems that allow flip chip assembly.
New designs and methods are needed to mitigate these deficiencies so that flip chip integration of RF and MMW GaAs microchips can be utilized.